1. Field of the Invention
The present invention generally relates to the packaging of semiconductor chips. More particularly, the present invention relates to wafer level packages, multi-package stacks of wafer level packages, and methods of manufacturing wafer level packages and multi-package stacks.
2. Background of the Invention
The miniaturization of electronic devices has led to the development of different techniques for containing semiconductor integrated circuit (IC) chips in smaller and smaller packages. The Joint Electronic Device Engineering Council (JEDEC) has proposed the name “Chip Scale Package (CSP)” to denote a semiconductor chip package which is nearly as small as the semiconductor chip itself. In particular, the JEDEC defines CSP as a package having an outline that is 1.2 times or less the outline of the semiconductor chip contained in the package. CSP technology is suitable for packaging ICs used in electronic products such as digital camcorders, notebook computers and memory cards. Specifically, major applications of CSP technology include digital signal processors (DSPs), microprocessors, application specific integrated circuit (ASICs), dynamic random access memories (DRAMs), and flash memories.
One disadvantage of CSP technology, however, is that the packages are relatively expensive to manufacture, especially when compared to more conventional and commonly used plastic packages, such as a ball grid array (BGA) package and a thin small outline package (TSOP).
In an effort to reduce costs, wafer level package (WLP) technology has been proposed. Wafer level packages are formed at the wafer level (thus reducing costs), and then diced into individual devices. The packages themselves are characterized by external terminals, such as metallic solder bumps or balls, that are distributed in a two-dimensional array over a bottom surface of the package. This reduces the signal path of the semiconductor chip to a package I/O location, thereby improving the operational speed of the device. Further, unlike other chip packages having peripheral leads extending from the sides of the package, the WLP occupies no more of the surface of the printed circuit board (PCB) than roughly the size of the chip itself.
FIG. 1 is a plan view illustrating a portion of a conventional WLP 20, and FIG. 2 is a cross-sectional view taken along the line I–I′ of FIG. 1. A semiconductor integrated circuit chip 14 includes a plurality of chip pads 11 and a passivation layer 13 on a semiconductor substrate 12. The passivation layer 13 is formed of silicon oxide, silicon nitride or a composite layer thereof. The chip pads 11 are formed of aluminum. A first dielectric layer 22 of polyimide is formed on the semiconductor chip 14. A plurality of metal trace patterns 21 is formed on the first dielectric layer 22. Each of the metal trace patterns 21 contacts a corresponding one of the chip pads 11. A second dielectric layer 24 is formed on the metal trace patterns 21 and the first dielectric layer 22. The metal trace patterns 21, the first dielectric layer 22 and the second dielectric layer 24 constitute a rerouting layer 21′. A plurality of solder balls 28 are placed on the other end of the metal trace patterns 21. Subsequently, the resultant structure is subjected to a reflow process to join the solder balls 28 onto the metal trace patterns 21.
Unfortunately, however, the solder ball joints tend to be unreliable. A primary reason for this is the stresses that result from the difference in coefficients of thermal expansion (CTEs) of the WLP 20 and an external printed circuit board (PCB). That is, typically the WLP is mounted to a PCB such that the solder balls of the WLP are connected between the WLP and the PCB. The semiconductor chip 14 heats up when electrical power is dissipated during operation, and then cools down when not operating. The different rates of expansion of the WLP and PCB connected at opposite sides of the solder balls create mechanical stresses within the solder balls, sometimes resulting in fissures and other defects.
In the meantime, recent proposals include the stacking of plural wafer level packages to form a multi-package stack for mounting on a single printed circuit board.
For example, U.S. Pat. No. 6,429,096 is directed to a conventional method of forming a multi-package stack 10 as shown in FIG. 3. At the wafer level, apertures are formed through a semiconductor wafer, and the apertures are filled with conductive plugs 2. The semiconductor wafer is then diced and divided into a plurality of packages 1. At least two of the packages 1 are stacked through use of bumps 3 connected between the plugs 2 of adjacent packages, thereby forming the multi-package stack 10. The multi-package stack 10 is mounted on the landing pad 5 of an external PCB 4 through use of the bumps 3a at the bottommost package 1a. 
Again, however, there is a difference in the coefficients of thermal expansion (CTEs) of the bottommost package 1a and an external printed circuit board (PCB). As a result, the joints formed by the solder balls 3a are unreliable and prone to failures.